In order to enable higher port-count components, Gigabit Ethernet (GE) Media Access Control (MAC) to physical layer (PHY) integrated circuit (IC) connections have evolved from wide parallel interfaces such as those defined in various specifications of the Institute of Electrical and Electronics Engineers (IEEE) to higher-speed narrower interfaces. Current state of the art communication devices use a single serial lane MAC-PHY connection per GE port, for example, and PHY devices typically come in densities of four and eight ports per chip. As switch ICs, MAC ICs, and other devices increase in bandwidth to 40 Gigabits per second (Gb/s) and beyond, the current techniques of using a separate PHY connections for each port is not economical and does not scale.
For devices that can support both high- and low-speed ports such as GE ports and 10GE ports, there is also an additional cost associated with providing respective different interfaces for the different port types. In accordance with conventional techniques, ten separate GE connections and one 10GE connection would be provided to a PHY device to allow a GE/10GE capable MAC device to be used in conjunction with ten GE ports or a single 10GE port. A standard interface architecture for enabling both port types does not currently exist.
Thus, there remains a need for improved interfaces and related interface techniques.